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bemoon
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Joined: 2017-07-19 09:37
About GP_ADC 3.3Msps sample rate

According to DATASHEET :
"The conversion itself is fast and takes approximately one clock cycle of 16 MHz, though the data handling will require several additional clock cycles, depending on the software code style. The fastest code can handle the data in four clock cycles of 16 MHz, resulting to a highest sampling rate of 16 MHz/5 = 3.3 Msample/s."


register int i,j,k;
k = GP_ADC_RESULT_REG;
j = 0x4C03;
i = GP_ADC_CTRL_REG;

*( volatile uint16*)(i) = j;
__nop();
__nop();
__nop();
__nop();
k = *( volatile uint16*)(k);

I'm using above code to get the most simple ASM code, maybe the fastest code .
But I have to wait 4 NOP after write to GP_ADC_CTRL_REG to get the right ADC_RESULT.
Could anyone tell me What happened when cpu has been idled for 4 HCLK cycles?
and, what kind of Code style can exceed the top performence of the internal ADC?

Device: 
PM_Dialog
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Last seen: 27 min 26 sec ago
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Joined: 2018-02-08 11:03
Hi bemoon,

Hi bemoon,

The ADC consists of hold and sampling phase. This means that the ADC should wait to the source for an amount of time in order to do the correct estimation of voltage. The conversion stage will  take 1 clock cycle but he sampling depends on what you are trying to sample. You should wait more 1 clock cycle for the sampling.  When you added 4 NOP , are you getting the correct results? In the IDLE stste, the CPU does nothing, just waits.

Thanks, PM_Dialog

bemoon
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Last seen: 6 months 5 days ago
Joined: 2017-07-19 09:37
Hi PM,

Hi PM,
Thank you for your detailed answer.
I studied the AMBA Bus system for few days, and got a speculate.
According to the datasheet, Cortex M core connects to the AHB bus as a master, and ADC ,as a peripheral, is connected to APB bus which can communicate with core via APB Bridge. So when we use LDRH or STRH instructions to READ or WRITE the ADC control/result register, the core must perform the AHB Bus protocol timing and indirectly make the APB Bridge works as well. The whole sequence is like this (steps are synchronized by HCLK):
For STRH :
1. Core set HADDR and HWRITE. APB Bridge is in IDLE state.
2. Core set HWDATA . APB Bridge go to WRITE WAIT state.
3. Core wait . APB Bridge goto WRITE state.
4. Core wait. APB Bridge goto WRITE ENABLE state
For LDRH:
1. Core set HADDR and reset HWRITE. APB Bridge is in IDLE state.
2. Core wait . APB Bridge go to READ state.
3. Core wait . APB Bridge goto READ ENABLE state.

I put all the corresponding items in one table:


HCLK=16Mhz; One cycle = 62.5ns.
Instruction : STRH NOP NOP NOP NOP LDRH … … …
AHB Bus state : ADDR DATA WAIT WAIT WAIT ADDR DATA WAIT WAIT
APB Bridge state : IDLE W_WAIT WRITE W_ENABLE IDLE IDLE READ R_ENABLE IDLE
GP_ADC_CTRL_REG: 4C01 4C01 4C01 4C01 4C03 4C03 4C11 4C11 4C11
ADC state : Tracing Tracing Tracing Tracing Conversion ( 65ns ) Tracing Tracing Tracing

I guess that is the reason why we need 4 NOP to get the correct result.
I don't know why the code tag doesn't work,The table looks unreadable ,So I attached it.

Attachment: