JTAG SWDIO SWCLK access after PLT programming

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dlo
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JTAG SWDIO SWCLK access after PLT programming

I have a few units that has gone through production and have had their OTP memory programmed. No flash on board. In the configuration XML I have specified enable JTAG, but when I'm trying to reprogram the RAM of a unit via JTAG, I am not getting any communications on SmartSnippets Toolbox... is my understanding of JTAG enable in the configuration wrong?

 Thank you,

Device: 
LC_Dialog
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Hi dio,

Hi dio,

If the Enable flag is set duirng the OTP programming, it should be available for later use. Can you elaborate on how you are trying to access the JTAG from the SS Toolbox. Are you using a dev kit and connecting the jtag pins to your custom hardware or by some other means? Also, did you happen to disable the "CFG_DEVELOPMENT_DEBUG"?

Best,
LC_Dialog

dlo
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Hello LP,

Hello LP,

 

I did undefine CFG_DEVELOPMENT_DEBUG.

#undef CFG_DEVELOPMENT_DEBUG

 

I am using a Segger JLINK wired to SWDIO and SWCLK as well as GND.

 

Thank you for the support.

LC_Dialog
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Hi dio,

Hi dio,

Is there a VCC connected. 
Would you be okay to share the XML config file.

Best,
LC_Dialog

dlo
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The unit is powered with a

The unit is powered with a coin cell and I can see it on my BLE beacon scans, so I figured I didn't need to connect Vtarget to JLINK and just ignore the error about no voltage detected. 

Attached is my XML generated from the PLT CFG, please rename to XML since the uploader doesn't allow XML formatted files.

Attachment: 
dlo
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Good call on the VCC, I seem

Good call on the VCC, I seem to be able to talk to it now, but still not able to load code:

[INFO    General           @19-08-15 20:21:38] TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
[INFO    General           @19-08-15 20:21:38] TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
[INFO    General           @19-08-15 20:21:38] Found SWD-DP with ID 0x0BB11477
[INFO    General           @19-08-15 20:21:38] FPUnit: 4 code (BP) slots and 0 literal slots
[INFO    General           @19-08-15 20:21:38] Found Cortex-M0 r0p0, Little endian.
[INFO    General           @19-08-15 20:21:38] BTLE device selected.
[INFO    Booter            @19-08-15 20:21:56] Found SWD-DP with ID 0x0BB11477
[INFO    Booter            @19-08-15 20:21:56] FPUnit: 4 code (BP) slots and 0 literal slots
[INFO    Booter            @19-08-15 20:21:56] Found Cortex-M0 r0p0, Little endian.
[WARNING Booter            @19-08-15 20:21:56] CPU could not be halted
[ERROR   Booter            @19-08-15 20:21:56] Failed writing value A4 at address 50000012.
[ERROR   Booter            @19-08-15 20:21:56] Failed downloading firmware file to the board.

LC_Dialog
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Hi dio,

Hi dio,

Thanks for sharing the config file. At a quick glance, it looks to be correctly configured for jtag.
And the log indicates, that it cannot do a reset since the CPU cannot be halted. Just to isolate the different factors, can you try and do this with a DA14580 dev kit motherboard by connecting the JTAG pins on the devkit to your customer hardware. 
Also, another quick trials and error approach can be, if you have the reset pin exposed, doing a reset just before accessing the chip via the jtag can give jtag time to grab and halt the CPU. This is remote possibility, but it did solve the issue sometimes.

Best,
LC_Dialog

dlo
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Thank you for the reply LC, I

Thank you for the reply LC, I'll test your suggestion next time. I was in a bit of a rush, so I decided to replace the DA14580 with a new one so I can flash new code to it.