PWM output become high level between one cycle.

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imaizumi.k
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PWM output become high level between one cycle.

Hello Dialog support team,

I want to change PWM duty dynamic(using Timer2).
There is phenom that PWM output become high level between one cycle.
I attach snapshot of PWM output.

I read "Figure 48: Timer 2 PWM Block Diagram" in DA14580 datasheet.
I think that this phenomenon is caused by a comparator of DUTY.
When T2_DUTY_CNTR equal PWM2_DUTY only, PWM output become Low level.
But when PWM2_DUTY set a value less than T2_DUTY_CNTR, PWM output keep High level between one cycle.

I think this phenomenon is occurring in the attached snapshot

Is this idea correct?
Could you tell me this workaround?

Best Regards,
Katsutoshi Imaizumi,

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PM_Dialog
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Hi imaizumi.k,

Hi imaizumi.k,

This phenomenon sometimes happens when you change the pwm duty cycle to a lower pwm duty cycle, because the new pwm duty cycle has to wait until the timer2 goes to zero. So, if you change the duty cycle to a lower one, and the timer will not be to zero, you while see a high level between one cycle. A theoretical work around will be to zeroing the timer2 and add a small delay (for example 3 NOP) before you change the duty cycle.

Thanks, PM_Dialog

imaizumi.k
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I understood that I have to

I understood that I have to wait until the timer2 goes to zero before change DUTY.
But I don't know to watch the timing that the timer2 goes to zero.
Because T2_DUTY_CNTR and T2_FREQ_CNTR are internal registers, so 14580 core can't read it.

Could you tell me how to confirm timer2 counter?

Best Regards,
Katsutoshi Imaizumi

PM_Dialog
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Hi imaizumi.k,        

Hi imaizumi.k,        

Could you please clarify your question? As I mentioned in my previous post you should add a small delay (for example 3 NOP) before you change the duty cycle. So, do you want to know the duration of the delay?

Thanks, PM_Dialog

imaizumi.k
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Sorry, but I couldn't

Sorry, but I couldn't understand the meaning that "work around will be to zeroing the timer2" .
Which does it means " Timer2 counter to be zero" or " Timer2 to stop" ? Or other meaning?

If it means "Timer2 counter to be zero", please tell me the method.
If it mean2 "Timer2 to stop", I understand it is " Timer2 stop-> 3NOP ->Duty change ->Timer2 start".
But when I do timer2 to restart, timer2 cycle timing change.
I do not want to change the timing of PWM, I want to change only DUTY of PWM.

Colud you tell me the answer of my question?

Best Regards,
Katsutoshi Imaizumi,

PM_Dialog
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Hi imaizumi.k,

Hi imaizumi.k,

Apologies for the delay. You should set the timer into zero and add a small delay, so it is not needed to stop the timer. Could you please let me know if you would like any guidance on this? Did you set the timer into zero?

Thanks, PM_Dialog

imaizumi.k
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Thank you for your response.

Thank you for your response.
I'd like to know the guidance to set timer2 into zero without stopping timer.
Please tell me how to do it.

Best Regards,
Katsutoshi Imaizumi

PM_Dialog
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Hi imaizumi.k,

Hi imaizumi.k,

Could you please upload the code snippet that you are using? After that I will review it and I will get back to you as soon as possible.

Thanks, PM_Dialog

imaizumi.k
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I attached the source code

I attached the source code that caused the phenomenon.
It's the sample source "timer2_pwm" besed.
I modified it to shorten the duty setting timing.

Could you review the code?

Best Regards,
Katsutoshi Imaizumi

PM_Dialog
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Hi imaizumi.k,

Hi imaizumi.k,

Thanks for uploading your code. Let me check your project and I will get back to you as soon as possible.

Thanks, PM_Dialog

PM_Dialog
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Hi imaizumi.k,

Hi imaizumi.k,

The delay that you are using is you are using is too short, so I would highly recommend you to use the default delay (1 second) as the example of the SDK.

Thanks, PM_Dialog