Question about Timer0 ON counter and instruction cycles

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bemoon
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Question about Timer0 ON counter and instruction cycles

Hi !
I designed a test about DA14580's Timer0 ON counter , in order to verify Timer0's working mechanism.

The initiation of timer 0 is :

#define PWM_HIGH 7

set_tmr_enable(CLK_PER_REG_TMR_ENABLED);
set_tmr_div(CLK_PER_REG_TMR_DIV_1);
timer0_init(TIM0_CLK_FAST, PWM_MODE_ONE, TIM0_CLK_NO_DIV);

time0on = ((PWM_HIGH+1) * 2)*1 -1; // make timer0 on counter = high + low
timer0_set(time0on, PWM_HIGH, PWM_HIGH);

timer0_start();

I got an 1Mhz PWM0 and PWM1 and an 1Mhz ON counter interrupt request.

The On counter test is :

register uint16 i,j,k;
i = *( volatile uint16*)(TIMER0_ON_REG);
j = *( volatile uint16*)(TIMER0_ON_REG);
k = *( volatile uint16*)(TIMER0_ON_REG);

The i,j,k output via UART after they got the TIMER0_ON_REG value.
Then I got the results :
i= 0003
j= 0000
k=000D

Keil gives ASM code of above code segment :

155: i = *( volatile uint16*)(TIMER0_ON_REG);
0x20000BCC 4826 LDR r0,[pc,#152] ; @0x20000C68
0x20000BCE 8845 LDRH r5,[r0,#0x02]
156: j = *( volatile uint16*)(TIMER0_ON_REG);
0x20000BD0 8846 LDRH r6,[r0,#0x02]
157: k = *( volatile uint16*)(TIMER0_ON_REG);
158:
159:
0x20000BD2 8847 LDRH r7,[r0,#0x02]

It seems that CPU runs as below sequence:
1 .load Timer0 ON Counter Register's Address to R0
2. Load the Timer0 ON Counter value to R5 (i);
3. Load the Timer0 ON Counter value to R6 (j);
4. Load the Timer0 ON Counter value to R7 (k);

According to ARM Cortex-M0 instruction summary, LDRH costs 2 clock cycles.
My question is if R5(i) got ' 0003' , after 2 clock cycles R6(j) should get '0001' and the same reason ,R7(k) shout get '000F'.
Is there something wrong in test design or something misunderstood about Timer0?

I attached the whole project. Plz verify it. Thanks a lot!

Attachment: 
Device: 
bemoon
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Joined: 2017-07-19 09:37
Datasheets shows that Timer 0

Datasheets shows that Timer 0 connected to the APB bus and communicate with AHB bus via APB bridge.
ARM Cortex M documents shows:
For a system with HCLK equal to PCLK, and if there is no error response from APB slaves, the minimum number of cycles for each RW is as follows:
Three HCLK cycles when REGISTER_RDATA is 1.
Two HCLK cycles when REGISTER_RDATA is 0.

So, a LDRH instruction on TIMER0_ON_REG costs 3 clock cycles.
Am I right?

PM_Dialog
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Hi bemoon,

Hi bemoon,

Yes, you are right. According to the ARM Cortex M0 instruction set, when the REGISTER_RDATA (Verilog parameter) is set to 0 the latency of APB accesses is reduced. This results in the read data from the APB slaves, PRDATA, being directly output to the AHB read data output, HRDATA, and reduces the wait states in addition to the gate counts. By default, the REGISTER_RDATA parameter is set to 1 to include a registering stage. So, you will have 3 HCLK cycles when REGISTER_RDATA is 1, and 2 HCLK cycles when REGISTER_RDATA is 0

Thanks, PM_Dialog

bemoon
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Last seen: 6 months 1 week ago
Joined: 2017-07-19 09:37
Thank you for your response.

Thank you for your response.
The REGISTER_RDATA is a Verilog parameter,means that it effected in RTL design of this IC, and no chance for end-user to change it.
So the DA14580 must costs at least 3 HCLK to access APB bus device.
Is it right?
Thanks again!

PM_Dialog
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Hi bemoon,

Hi bemoon,

If the REGISTER_RDATA is 1, yes it costs at least 3 HCLK to access APB bus device.

Thanks, PM_Dialog