Dual voltage GreenPAK designer bug?

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peter_ibeat
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Dual voltage GreenPAK designer bug?

When designing with a dual voltage GreenPAK, it looks like all GPIOs are tied to VDD, instead of certain ones tied to VDD2. Is this a designer bug?

See attached PDF (screenshot).

 

 

Thanks,

Peter

 

Device: 
Device Number: 
SLG46538
pavloZ
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Last seen: 2 years 6 months ago
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Joined: 2018-01-31 12:50
Hi Peter,

Hi Peter,

no, this is not the designer bug. The connection you have shown is internal logic connection to OE. VDD2 is dedicated mostly to PIN's output MOSFETs.

peter_ibeat
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OK, that makes sense. What

OK, that makes sense. What about configuring one of those pins as an input with a pullup? Is it pulled to VDD or VDD2?

pavloZ
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The pullup resistors on VDD2

The pullup resistors on VDD2 side are connected to to VDD2 as well. This is illustrated on GPIOs internal diagram at the datasheet.