Emulation output and simulation output do not match

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ajeya
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Emulation output and simulation output do not match

My emulation output and actual output does not match when using
GreenPak software 6.14
SLG 46110V STQFN 12 socket

attachment has measured output images

Device: 
Device Number: 
SLG 46110V
PavloZ
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Joined: 2018-01-31 12:50
Hi ajeya, thanks for your

Hi ajeya, thanks for your question. You have wrong CNT/DLY0 connection in the design. OSC OUT1 is connected to DLY_IN of delay block, so this block is being resetted all the time.

1. If you need start-up delay you can connect DLY_IN of CNT/DLY block to POR block; set CNT/DLY as DELAY, edge select as RISING.

2. If you need to use CLK/3 division you can set CNT clock source as Ext.CLK and connect CLK input toOSC OUT1 output.

If you some complete solution, could you, please, share full applicaton requirements of timing diagram input to output.

Thanks a lot for your attention.

ajeya
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Last seen: 3 months 2 weeks ago
Joined: 2018-09-17 22:12
Pavloz,

Pavloz,

I have emailed my requirement last 2 days back and waiting for a reply.

ajeya
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Last seen: 3 months 2 weeks ago
Joined: 2018-09-17 22:12
POR Block has only output how

POR Block has only output how to send input of CNT to POR?

PavloZ
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Last seen: 2 days 15 hours ago
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Hi ajeya,

Hi ajeya,

yes Power-On Reset block(POR) has only output, and it goes high after some delay  during stsrt-up. If you need to create some power-on sequence (e.g. 1.5ms delay) just connect POR output to CNT/DLY block DLNY_IN input.