Field-Update of SLG46824/6 used as power sequencer

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pkrmht
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Last seen: 2 years 7 months ago
Joined: 2020-01-09 13:40
Field-Update of SLG46824/6 used as power sequencer

Dear Forum

My intention is to use SLG4682x as power sequencer in our newest Zynq MPSoC design.
Initial NVM programming will be done during production test through testpoints on I2C with the MPSoC unpowered.

In the product, the I2C-bus is controlled by MPSoC as master and available only after the SLG4682x controlled power sequencing. Therefore a field update becomes risky if the NVM programming is interrupted by a power fail: The sequencing will not work due to the now corrupted NVM and the mentionned testpoints are not accessible in the field.

What is your suggestion to solve this issue? Is there an AN or possibly some white paper dealing with it.

Ideal would be the possibility to boot the device from the EEPROM (e.g. by a single bit switch) until the NVM-Update had been verified as a whole and considered good. But as I understand from the datasheet, the EEPROM is just accessible over I2C and completely unrelated to the CPLD functionality. Am i Wrong?

Thanks for your inputs in advance & best regards
Peter

Device: 
Device Number: 
SLG46826
ssaravan
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Last seen: 1 year 6 months ago
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Joined: 2019-10-01 13:53
Hi Peter,

Hi Peter,

Could you  clarify if there is a need to rewrite NVM, because to change the design it is enough to write registers, which are loaded from the NVM. If a rewrite is essential, is it needed for the entire chip(NVM) or just some parts (like DLY, LUTs)?

Thank you & Best Regards

Shivani

pkrmht
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Last seen: 2 years 7 months ago
Joined: 2020-01-09 13:40
Hi Shivani

Hi Shivani

My use case is that we might want to change the power sequencing structure at a later point of time (i.e. on a product in thie filed). Since the I2C master (MPSoC) is not present when power sequencing takes place, the idea is to rewrite the NVM, verify it and from the next power cycle it comes up with the new sequencing.

However, if I face a power loss during the mentionned update, I might have a big problem (i.e. a corrupted NVM image).
A comonly used strategy for such devices is to have two pages to load from with a switch in one defined position. So you can write the image into the second (not yet active) page, verify it and, if everything is good, switch the booting source with one atomic write access.

I hoped, that the EEPROM could be used for this purpuse, but after some more read-in to this device, I fear this is not possible and I have to look for a different recovery strategy.

Best regards,
Peter