Frequency Detector Block in Other GreenPAKs

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EE_Flames_fan
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Frequency Detector Block in Other GreenPAKs

Hello Dialog Semiconductor,

I've been testing a design with the SLG46826 and have been using the frequency detect mode in one of your counter blocks. I've been wanting to switch to the SLG46108 to save board space, but I'm noticing that it doesn't seem to have a frequency detection mode in the counters. Is there a GreenPAK this size that can do frequency detection? I don't need many more functions than that but the frequency detection is super critical.

Thanks in advance.

Device: 
Device Number: 
SLG46108V
PavloZ
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Hi EE_Flames_fan, thanks for

Hi EE_Flames_fan, thanks for a good question! You can easily implement frequency detector using edge detector and delay block falling triggered. Please see the attached draft for SLG46108 device.

EE_Flames_fan
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Excellent, I just tried this

Excellent, I just tried this with my project and it works perfectly. Thank you PavloZ!

ajeya
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This is edge detector and not

This is edge detector and not frequency detector right?

How does it detect frequency? I am not sure I understand?
New here.

ajeya
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I simulated the solution

I simulated the solution provided.

However,l I see two high's in the output from CNT block.

Please see attached.

PavloZ
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Hi ajeya, my design example

Hi ajeya, my design example is the simpliest frequency detector, when input signal period is higher than delay block time then output is switching but when input period lower the output is high. Please try to change the input frequency at simulation and see how it works.

Attachment: 
ajeya
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My input signal is Umax=3.3

My input signal is Umax=3.3 Umin =0V
Umax time 500us
Umin time 500us
Typical delay time of Delay block = 4.04ms

So the input signal period (1ms) < CNT period (4.04 ms) is

Why did my output switch?
I must be missing something here.

PavloZ
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Hi ajeya, please see

Hi ajeya, please see attachment. Do you have the same design? P DLY output is switching and CNT/DLY0 outptut goes high and keep.

Attachment: 
ajeya
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Hi Pavloz,

Hi Pavloz,

From the image provided in your attachment titled 108 freq, it shows CNT/DLY output low, in the beginning, rising to give a pulse and goes down to zero, and after some time again coming rising up to high. Thereafter, it stays high.
How to avoid the first pulse?

Thanks,

Ajeya

PavloZ
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Hi ajeya, it depends on your

Hi ajeya, it depends on your application requirements. To add start-up delay for example.