Hi,
I intend to use SLG46826V to design a CLK buffer to generate 25MHz waveform with 50% duty circle
however, the output seems not what I' expecting.
Attached is the design with waveforms.
Could you please advise?
Device:
Device Number:
SLG46826V
Hi,
Thank you for reaching out to us.
The absence of square pulse on the output could be due to the parasitic capacitance.
Push-Pull output, board, socket, and scope probes create the parasitic RC circuit. RC circuit needs some time to be charged. The more components on the way to your scope, the higher capacitance, the bigger time constant (T=R*C).
If you want to see the square pulses you need to program the chip, solder it on PCB, and use the specific equipment, short line with connectors (like SMA connectors) and impedance matching, etc. In simple terms, you may need to decrease the C component from the equation T=R*C. Please let me know if this helps
Kind Regards
Shivani
Hi Shivani,
Thanks for the advise.
Based on your explanation above, can I conclude that the setting of the OSC is correct (the predivider and Output set to 1)?
Thanks
Hi,
Yes the current setting is right. The CLK predivider and OUT divider can be used if you further want to significantly reduce the value
Kind Regards
Shivani