I'm missing data in the datasheet about the latchup resilience of the low voltage IO pins, and in particular the pins with an output fet structure directly connected to it.
I am in a situation where I cannot guarantee that all IO pins have a lower or equal voltage than the VDD pin. during powerup one pin may go higher and possible trigger latchup.
Usually latchup sensitivity is defined by the maximum current through the Pfet body diode or guardring, when a pin is pulled above the vdd.
what value has that current ?