latchup resilience of IO pin

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koen@weijand.nl
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Joined: 2015-05-14 08:10
latchup resilience of IO pin

I'm missing data in the datasheet about the latchup resilience of the low voltage IO pins, and in particular the pins with an output fet structure directly connected to it.

 

I am in a situation where I cannot guarantee that all IO pins have a lower or equal voltage than the VDD pin.  during powerup one pin may go higher and possible trigger latchup.

 

Usually latchup sensitivity is defined by the maximum current through the Pfet body diode or guardring, when a pin is pulled above the vdd.

 

what value has that current ?

 

 

Device: 
Device Number: 
SLG47105
olehs
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Last seen: 1 year 7 months ago
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Joined: 2018-02-07 11:40
Hi koen@weijand.nl,

Hi koen@weijand.nl,

Sorry for the delayed reply, 

All GPAK pass at least +/-100mA Latchup test. Please note that the datasheet includes Absolute Maximum Ratings for inputs to have a maximum 1mA into the pin. This is not related to latch-up, but to prevent too much current from to flowing into substrate junctions which may disturb other circuitry, leading to the wrong operation which can potentially lead to damaging system situations, such as a GPIO configured as input getting flipped to become output which fights external driver, etc.  If VDD is completely powered off, all circuits are forced off, so 1mA does not apply to this situation. However, care should be taken when part turns on not to have a forward bias situation >> 1mA.

Best regards, 

olehs