NVM life expectancy when using I2C

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peterpotnin
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NVM life expectancy when using I2C

Hello,
I'm designing what's essentially an I2C-to-PWM output driver, based on SLG46533.

For PWM, I'm using a DFF+Delay circuit described in September 2018 GreenPAK Cookbook, page 38: "Technique: Setting a Constant Duty Cycle". To control the PWM duty cycle, I use an idea from Application Note AN-1144 "I2C IO Controllers 8-bit BUS". I update CNT/DLY module's Counter Data via I2C by sending a command to modify the appropriate registers; for example, CNT2/DLY2 in SLG46533 is reg<1543:1536>. This solution works great in emulation, but...

My question is: every time I modify the Counter Data - am I rewriting the NVM? Is there a limit to how many times I can do this? Is there perhaps a more elegant way to control up to 3 PWM outputs' duty cycles via I2C?

I'm attaching my design to this message, too

Thanks!

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SLG46533
PavloZ
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Hi Peterpotnin, you can also

Hi Peterpotnin, you can also see https://www.dialog-semiconductor.com/sites/default/files/an-cm-248_pwm_c... PWM implementation. All counter data changes are in electric dependent memory, so after the chip reset all the registers are copied from the NVM again. Those registers like RAM have huge count of writing cycles. 

peterpotnin
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Thank you guys for being so

Thank you guys for being so responsive and knowledgeable! In addition to PavloZ's answer, here's what I got from Dialog's Alex Richardson over email (which solves my predicament):

The short answer is that when you re-write the counter data you aren’t rewriting the NVM, and there isn’t an ostensible limit to how many times this can be done.

All of our devices have two layers to the programming; the NVM layer and a register layer. The registers are loaded during the POR sequence with the data in the NVM. Our OTP devices with I2C compatibility can have their registers re-written, but on a power cycle they will re-load the original data from the NVM. The SLG46533 is an OTP device, so with your current design this would be the expected behavior.

Our MTP devices, the SLG46826 and SLG46824, can have their NVM re-written in addition to their registers, but they have an endurance limit of 1000 NVM write cycles