SLG47105V ldle current

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koen@weijand.nl
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SLG47105V ldle current

have a fresh naked chip on a testboard, nothing connected but VDD and I2C. emulated the chip using the I2C serial debuger board ext supply,  and vcc current  ends up to  32.6mA@3V after hitting the emulation button; after removing the I2C the current is still there. it does ot run through any pin.

I can monitor the sleep pin of HV drivers  at an IO pin, and that is high,  HV driver pins are highZ. the osc is also forced using the same  net to power down. confirmed off/powered down.

 

all IO's are either 0 or high, no halfway levels.  when the HV output is not in  sleep but disabled, the output pins are 0.3V above the rail or gnd. most likely some leakage from the gate drive charge pump.

 

but where does the 32mA go ? is it possible to short some internals by improper programming code ? I'm i the beta tester here ? it is suply dependent, goed up when VDD goes up.

in my case the VDD and HVvdd are the same net.

help is appreciated...

Device: 
Device Number: 
SLG47105V
koen@weijand.nl
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whne I remove the HVVD1 and 

whne I remove the HVVD1 and  2 from the VDD rail, and then emulate , the current is gone, also when I connect the HVVD1 and 2 to the  VDD afterwards .

koen@weijand.nl
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when HVVD2 adn VDD are

when HVVD2 adn VDD are disconnected during emulation transmit, the current stays low.

ssaravan
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Hi ,

Hi ,

Thank you for reaching out and for the detailed examination of the 47105V chip. Could you let me know how the current was measured here?

Kind Regards

Shivani

koen@weijand.nl
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a non programmed device seems

a non programmed device seems un responsive, does it need to be programmed first to be able to emulate using the serieal debugger ?  the dev board emulation does all sorts of "above rail" signaling, plus I2C.  this is the command that the debuggers sebds ou, but no response form the 47105V. does the VDD2 need to be connected ?

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koen@weijand.nl
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total current VDD + vdd2,

total current VDD + vdd2, measured by IT6412 precision source

koen@weijand.nl
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the thermal pads are not

the thermal pads are not connected for simplicity as the motor currents are < 100mA

koen@weijand.nl
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developing the program on the

developing the program on the dev board using the advanced dev platfrom had no problems.

koen@weijand.nl
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another thing that I noticed

another thing that I noticed is that there is a diode between VDD and VDD2 , so VDD2 is not allowed to be 0.6V  lower than VDD. this is not propely reflected in the datasheet. if this 0.6V does trigger parasitic devices is not stated either.

ssaravan
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Thank you for the feedback.

Thank you for the feedback. Chip current consumption should be measured via GND. Could you please attach the design file, so I can take a closer look

Kind Regards

Shivani

koen@weijand.nl
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encl the program, I can send

encl the program, I can send the schematic privately

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koen@weijand.nl
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on the dev board I supply 3V

on the dev board I supply 3V to the VDD2 nodes, and use the dev board 3V for VDD logic supply. UVLO on HV drive is disabled.

koen@weijand.nl
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there are only 2 connections

there are only 2 connections to the chip: GND  and VDD, VDD2 is wired to VDD on the PCB. current is measured as indicated by the precision  power supply (0.05% accuracy )

koen@weijand.nl
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chip rev 0x1  DB HW-FW: 1.3.1

chip rev 0x1  DB HW-FW: 1.3.1-2.8

ssaravan
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Thanks for the feedback.

Thanks for the feedback. Could you first program the chip and then measure the current? An empty chip can sometimes behave unusually

koen@weijand.nl
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a programmed chip does have

a programmed chip does have the problem. It appears that I have connected two IO ports to  the same voltage level as VDD , this is part of the intended design. the logic of the port is tristate or HI, so no conflict in a programmed state.

my guess is that the initiation of the chip is not properly done as it sees a conflict in the IO port halfway. that incomplete programming results in the high current state.