stepper motor circuit anomalies

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koen@weijand.nl
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stepper motor circuit anomalies

I edited the AN-CM-295 circuit and removed the current comparator circuit.

I set it to full step mode, but the circuit failed to operate.  I edited another vesion, placed the comparators  back edited the verison to full step only, removed the comparators, and miraculously that one could operate withput the CCMP .

I disabled the chopper by  connecting the CHOP input to gnd or leave unconnected.

apparently there are some forces at work that I have not yet identified.

 

 

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Device: 
Device Number: 
SLG47105V
olehs
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Hi koen@weijand.nl

Hi koen@weijand.nl

Thanks for the appeal!

I have a few questions regarding the anomaly:

1. Do you use stepper motor for the testing or you are just observing it on the scope without the hardware?

2. Does the initial design work fine, before you have made the changes? 

3. As far as I know, CCMPs in the design are dedicated to creating micro-step, so probably they are not necessary for full-step mode.

Best regards,

olehs

koen@weijand.nl
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I use a tiny stepper motor,

I use a tiny stepper motor, very low power (30mA/winding) .  the initial circuit works fine, I use it in full step mode. the deletion of the CCMP'S has apparently more impact somewhere else in the circuit. some hidden connections, or the microstep mode is not properly disabled when full step is chosen.

the luckiest choice of the chip design is the the UVLO on VDD2 is programmable. my vdd2 = 1.8V.

there is a hidden connection between the PWM and the PWM chopper, so these blocks are interlinked.

I tried tracing back the clock signal for the DFF1 and DFF2 that is missing when the CCMP's are deleted. suggestions welcome. this is my first HV GP design, done sofar lots with 46620 and on-board programmable ones.

olehs
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koen@weijand.nl,

koen@weijand.nl,

I can't understand where the problem is. Could send me please the waveforms of HV outputs. 

You said that your VDD2=1.8V, which is out of specification. Maybe this is the issue, outputs don't work fine because of VDD2 low level

Best regards, 

olehs

 

koen@weijand.nl
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oleh,

oleh,

there are no problems with the outputs. they work fine down to 1.8V (as the current is only 30mA) . i'm using the small eval brd. the signals to the HV out ctrl block signals are suddenly missing , basically the div/2 ff's have no signal. that is weird as I only have disabled the CCMP. disabling just one CCMP  (reset block all) disables both outputs. but I can't find any influence from the that signal into the signals driving the div2 FF's

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koen@weijand.nl
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correction, disabling the

correction, disabling the ccmp only disables the corresponding output.

olehs
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koen@weijand.nl

koen@weijand.nl

Thanks for sharing the files with me. 

I think I know what the problem is. When you reset the CCMP to default the Sleep input of HV output, which is shared with CCPM input, automatically connects to VDD. VDD connected to Sleep input means "force sleep", which disables the HV output. Please remove the VDD from all Sleep inputs and check the design again. 

Please let me know if the problem was solved. 

Best regards, 

olehs 

koen@weijand.nl
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I did compare the nvm files

I did compare the nvm files of the two designs, and just came to the same conclusion. checked the design and it works now, thanks for the help. quite confusing though ..

olehs
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koen@weijand.nl, 

koen@weijand.nl

Good to know that you found the solution to the problem!

Please let me know if you have any other questions about the GreenPAK.

Best regards, 

olehs