Total delay when configured as a level shifter

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Last seen: 3 years 3 months ago
Joined: 2019-06-01 21:56
Total delay when configured as a level shifter


I'm trying to estimate the total delay from an input pin to an output pin when configuring the SLG46539 as a dual-supply level shifter. The inputs will come from the low-voltage 1.8V domain (VDD2) and need to be level-shifted up to 2.7V - 4.2V (VDD). There should be no other logic or gates in this signal path. We can assume the output pin is driving a 10pF load.


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Last seen: 2 years 6 months ago
Joined: 2018-01-31 12:50
Hi Seth,

Hi Seth,

please refer to the base datasheet

Table 3. Typical Delay Estimated for Each Macrocell

to find exact combination of input/output and VDD.

Thanks for your question