Validate P-FET on SLG46127

⚠️
Hi there.. thanks for coming to the forums. Exciting news! we’re now in the process of moving to our new forum platform that will offer better functionality and is contained within the main Dialog website. All posts and accounts have been migrated. We’re now accepting traffic on the new forum only - please POST any new threads at https://www.dialog-semiconductor.com/support . We’ll be fixing bugs / optimising the searching and tagging over the coming days.
5 posts / 0 new
Last post
Alistair
Offline
Last seen: 4 years 5 months ago
Joined: 2018-06-20 10:42
Validate P-FET on SLG46127

Hi there,

I've just obtained a development + socket kit for the SLG46127. I'm having difficulty confirming the functionality of the P-FETs even with a simple sample program - I don't appear to be able to get them to turn on.

Would it be possible to provide a sample program and setup that I can use to quickly validate their functionality via emulation/test mode?

Many thanks

Device: 
Device Number: 
SLG46127
JE_Dialog
Offline
Last seen: 1 year 1 month ago
Staff
Joined: 2013-12-05 14:02
thanks for your message

thanks for your message Alistair. I'll have one of the team take a look at this for you. 

Yurii Shchebel
Offline
Last seen: 2 years 8 months ago
Joined: 2017-11-02 21:27
Hello Alistair,

Hello Alistair,

The SLG46127 has a dual-channel, 44 mOhm PMOS power switch designed to switch 1.71 to 5.5 V power rails up to 2 A per channel.
Each P-FET Power Switch can be controlled internally via the ONx digital input of the P-FET Power Switch component in GreenPAK Designer or externally via PWR_SW_ONx. Whether controlled externally or internally, a low signal on either ONx or PWR_SW_ONx will close the P-FET Power Switch.
Each P-FET Power Switch need not be used in the same voltage domain as VDD. However, when VIN is not tied to VDD, using a large pull-up resistor on PWR_SW_ON0 and PWR_SW_ON1 is recommended to prevent current from flowing through the P-FET Power Switch while the device is not powered.

I've attached a zip archive which includes a simple design (you can use it in the emulation or test mode), SLG46127V datasheet and P-FETs block diagram. Please let us know if you have more questions.

Best regards,
Yurii

Attachment: 
Alistair
Offline
Last seen: 4 years 5 months ago
Joined: 2018-06-20 10:42
Hi Yurii,

Hi Yurii,

Thanks for the program. This is similar to the program I've been testing so I don't think I'm making an error in the designer. Are you able to confirm a quick way to validate the functionality? For example via the buffered LEDs or a simple circuit? I have tried placing a simple 15Ohm load on VOUT and a 3v voltage source on VIN but am not seeing what I expect so it would be helpful if you could confirm a simple test circuit and the expected output/behaviour to confirm that the P-FETs are working as expected.

Many thanks

Alistair
Offline
Last seen: 4 years 5 months ago
Joined: 2018-06-20 10:42
Hi guys,

Hi guys,

My issue was not realising that I can only test the FETs using the pins on the socket board and not on the dev kit itself. Also the numbering is a bit confusing, the software / datasheet uses the terms VIN0/1 and VOUT0/1 but the socket board uses VIN1/2 and VOUT1/2.

Everything seems sorted now thanks.