Capacitor Selection Criteria

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electronherder
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Capacitor Selection Criteria

I am interested in using the DA9062 PMIC for a Zynq 7010 product. The data sheet has recommendations for capacitors, but I did not see much information about the requirements for them, such as min/max capacitance, package size, quantity, ESR, ESL, etc. The datasheet says "When selecting a capacitor, especially ones with high capacitance and small size, the DC bias characteristic has to be taken into account". I understand what DC bias is, so this suggests it is possible to use alternate components than those recommended. But I would like to understand what the limitations are.

Were the recommended components chosen to illustrate how small the PCB layout can be? Or were they chosen because the small package sizes would have a lower mounted inductance? Were multiple components used in parallel to further reduce the ESR and ESL? Or were multiple smaller values used to provide flexibility in reducing the number of capacitors used in production? Is there a maximum amount of capacitance that can be used?

Xilinx recommends certain values for the Zynq 7010, such as 100uF for bulk capacitance. If possible I would like to use the same capacitors for the PMIC regulators. I have 100uF 1206 capacitors, which I hope will work well because capacitors are very hard to procure these days!

Thanks,

ElectronHerder

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Hello ElectronHerder,

Hello ElectronHerder,

 

Let me talk with the team and get back to you.

 

Kind regards,
Elliott Dexter 

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Hello ElectronHerder,

Hello ElectronHerder,

We state in the DA9062 datasheet the tolerances for Capacitor's, ESR and Inductors (I have attached an example image), they can be found in the electrical characteristics part of the datasheet. Some of these parameters are not listed in the "component selection" section; this section is for specific recommended components. The components we recommend have been chosen for a small PCB sizem whilst maintining performance. 

Kind regards,
Elliott Dexter 

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electronherder
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Thank you Elliot for pointing

Thank you Elliot for pointing that out. I'm sorry I didn't see it. In the past I have used a lot of Texas Instruments parts, and their data sheets usually have a section on component selection that includes formulas and a description of the limitations. I guess I'm a creature of habit, and didn't think to look in the in the Electrical Characteristics section.

Is the output capacitance requirement based on full load? For example, if Buck 1 is operating in full-current mode but only driving 1.25A maximum, would the required capacitance be less? I'm not asking for specific numbers, just a generalization. How much of the capacitance is needed for stability vs. meeting minimum ripple specs?

Why is there a max spec for the output capacitor? What happens when you have too much capacitance? Does it become unstable? The regulator will be supplying current to a circuit that includes a significant amount of decoupling capacitance, so I am assuming that this must only be referring to the capacitors that are physically very close to the inductor.

Here is a link to the data sheet for the 100uF capacitor that I am using:

http://www.samsungsem.com/kr/support/product-search/mlcc/__icsFiles/afie...

I'm not exactly sure how to apply the ESR graph to the DA9062 ESR spec. The spec says "f > 100 kHz", which I take to mean all frequencies above 100 kHz. Is that right? I'd say this capacitor is pretty close to meeting the spec at 100 MHz. I believe your reference design uses two capacitors in parallel to halve the ESR and impedance. If I use this capacitor do you see any issues? How much benefit is there in using two capacitors in parallel?

Thanks and best regards,

ElectronHerder

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Hello ElectronHerder,

Hello ElectronHerder,

 

The recommend output capacitance is based upon full load. That’s why we have listed two different sets of recommended capacitors and their tolerances. Please see attached diagram for an example.

 

The main effect of increasing the output capacitance of the buck converter beyond the recommended maximum capacitance value would be an increase in buck start-up time and effect the slew rate. I cannot see why using 1 x 100 uF over 2 x 47 uF would greatly affect the start-up time. We chose to use two capacitors in parallel instead of one capacitor to reduce ESR, if the capacitor you plan on using is similar to our spec ESR then it should be ok.

 

The capacitor looks to be ok, however the link you sent me doesnt have the ESR over temperture.

 

Kind regards,

Elliott Dexter

electronherder
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Thank you Elliot. I'm not

Thank you Elliot. I'm not sure if your answer exactly addresses my question. The two sets of capacitor values are for two different operating modes of the device. In half-current mode, half of the pass devices are disabled, which means the output impedance is different than full-current mode. I was curious what the capacitor requirement would be for full-current mode, but at a maximum load of half the potential current. Sometimes I ask impractical questions to help me understand how things work.

Your answer about the main effect of increasing the output capacitance was enlightening. It appears the sequencing of the PMIC is based on time, not whether a voltage of one supply has been reached before starting the next supply. Kind of "open loop" instead of "closed loop". Is that a fair way to describe it?

Thank you for looking at the data sheet for the capacitor. I will see if I can find more data on ESR over temperature.

Kind regards,

ElectronHerder

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