DA7212- 200Hz noise generated from ADC

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akshay_pandit
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DA7212- 200Hz noise generated from ADC

Hi
I am experiencing 200Hz(Kind of Hissing noise) background continuous noise from adc. I have used MIC 1 in differential mode with mic bias of 2.5V and configuration are followed as per document attached.Would like to know the cause for noise generation from adc. Does noise pumping can introduce this kind of noise?

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ED_Dialog
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Hello,

Hello,
I think you might an issue with your CLK's. I have attached a script. The attached script uses minimal writes. I is for a MIC to ADC, bypassing the PLL.

1. Are you using a Dialog Eval board?

2. Could i see your schmatic?

Kind regards,
Elliott Dexter

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akshay_pandit
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Thanks for reply.

Thanks for reply.

I've tried bypassing PLL, but the observation is same. One change in my application is I2S word length per channel = 16 bits(Have made corresponding changes)
Following are CLK configuration of I2S,
I2S MCLK = 12.49 MHz
I2S WCLK = 48kHz

Even though mic is not connected to codec, noise is observed.
1. No, I'm not using eval board
2. PFA Sch of codec.

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ED_Dialog
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Hello,

Hello,

Using I2S MCLK = 12.49 MZ will not work when you bypass the PLL. We tried this set-up and noticed the noise. A standard MCLK will either be 12.288 or 11.2896MHz

The script we provided has the MCLK set to 12.49Mhz, we then use the PLL with the following settings and issue was resolved.

Kind regards,
Elliott Dexter

akshay_pandit
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Hi

Hi
Thanks for replicating the setup on your end.
I'm still facing same issue, even with PLL enabled in SRM mode(PLL_Status = 0x07) .
I was wrong on WCLK, the WCLK freq is 47.991kHz.

ED_Dialog
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Hello Akashay,

Hello Akashay,

You must ensure all Clocks are synced togther, as you might be losing the PLL Lock.

Kind regards,
Elliott

akshay_pandit
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PLL Lock has been achieved as

PLL Lock has been achieved as the PLL status shows 0x07. PLL status has been monitored for every 10s and every time it gives 0x07.

bmcadam
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Hello,

Hello,

Is everything working as expected now ?

Best Regards,