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mattlenz
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DA9063 Powerup

Hi,

we want to use a DA9063(+DA9210) pair to power a CPU Module. It is connected to a I/O Motherboard, which provides it with VSYS and a POWER ENABLE signal. VSYS will be valid before POWER ENABLE, but the exact timing is out of our control, typically we expect it to rise when all Motherboard supplies have been powered up.
Our idea was to connect POWER ENABLE to the SYS_EN input of the DA9063 and the CHIP_EN input of the DA9210, but that brings up the following issue: POWER ENABLE may already be high when the DA9063 has finished reading the OTP configuration, and SYS_EN is edge sensitive, so the DA9063 may not power up in this case.
I could not find information how long it takes for the DA9063 to reach POWERDOWN mode from NO-POWER.
Does somebody have a recommendation how to connect & configure the DA9063 so that POWER ENABLE can essentially be used as a level sensitive signal?

Thanks,
Matthias

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Hello Matthias,

Hello Matthias,

I am just trying to understand the set-up you require. What is Power enable, is it PWR_EN?

PWR_EN, SYS_EN and IC_EN are all inputs.

So VSYS is common for both the DA9063 and the DA9210. We can set the DA9063 to have the autoboot function, so it will boot-up at assertion of valid power supply level. We can then use the sequencer and the sequencer flags to create a mini sequence, we can then use the mini sequence set-up to enable the DA9210 and then wait for a response (Power Good signal) from the DA9210 to allow the PMIC to continue along the main sequence.

Kind regards,
Elliott Dexter

mattlenz
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POWER ENABLE is an external

POWER ENABLE is an external power enable signal connected to SYS_EN. Goal is to delay powering on the DA9063 and DA9210 until the motherboard has finished its powerup. So we do not want to start directly when VSYS becomes valid. The main issue is that the delay between VSYS and POWER ENABLE is unknown. If it is small, then the DA9063 may miss the rising edge of POWER ENABLE. If it is large (i.e. the DA9063 has reached POWERDOWN state), then it should work as expected. What we do not want is that the CPU module starts powering up as soon as VSYS is valid.

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Hi Matthias,

Hi Matthias,

Why not disenable Autoboot and use add a wake-up event to the SYS_EN GPI? So the PMIC is almost in a standby state waiting for the enable.

Kind regards,
Elliott

 

 

mattlenz
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Thank you Elliott.

Thank you Elliott.

That's almost exactly what I'm doing:

CONTROL_A.SYSTEM_EN = disabled

CONTROL_C.AUTO_BOOT = enabled

GPIO_8_9.GPIO8_PIN = GPI_SYS_EN

GPIO_8_9.GPIO8_TYPE = Active High

GPIO_8_9.WEN = Wakeup

Using this config, the DA9063 waits for a rising edge of GPIO8/SYS_EN and starts the power sequence. My fear (and I currently have no reasonable way of testing it) is that if the SYS_EN rising edge is too close to VSYS becoming valid, then the event will be missed and the DA9063 will not start. It definitely won't start if SYS_EN is high prior to VSYS.

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Hello Matthias,

Hello Matthias,

You will need to disable  AUTOBOOT. I would also recomend enabling the SYSTEM_EN register. This register is a target of the sequeincer, if you have GPI8_SYS_EN set, the PMIC will try and boot-up and aim for its target but will stop at the wait for GPIO8 to be toggled.

I cant think of a direct solution, I do have a slightly "out of the Box" solution.

Kind regards,

Elliott

 

mattlenz
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Hi Eliott,

Hi Eliott,

in my experiments on the evaluation platform, the PMIC did NOT stop and wait for GPI8_SYS_EN when SYSTEM_EN was set. I definitely had to disable it. I've attached my .ini file for your reference.

What's your slightly "out of the Box" solution?

Best,

Matthias

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Hello Matthias,

Hello Matthias,

I was slighly mistaken with saying enable SYSTEM_EN, I had my own logic slightly backward.

I have some comments on your ini file:

  • SYS_UP and PWR_UP should not be in the same slot.
  • WAIT_STEP has been added. Is this correct?

So my solution would be to use the GPIO_LEDs functon and connect the I/O to nONKEY. If the ENABLE signal comes after Vsys, then its ok. However if it comes before Vsys or at the same time and the PMIC miss the signal, then GPIO_LED signal will be enabled due to the voltage level on Vsys. We can use this signal to trigger a wake-on on nONKEY. We can then set the POWER_DOWN feature for nONKEY to a long delay.

Does this make sense?

Kind regards,
Elliott

 

mattlenz
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Hi Ellliott,

Hi Ellliott,

  • WAIT_STEP is correct. We enable an external power supply with GPO11 and wait for its power good signal on GPI10.
  • I'll move PWR_UP back one slot, but for our application there's really no difference between SYSTEM and POWER domain.
  • I'll play around with the GPIO_LED proposal. Certainly out-of-the-box thinking...

Thanks, Matthias

mattlenz
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Can't seem to get this to

Can't seem to get this to work. The nONKEY events do not override SYS_EN. Device State is Wait_Sys_En (31) until there is an actual rising edge on GPI8.

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Hello Mathies,

Hello Mathies,

Thats correct. The LED_PWM situation i described is for the intial start-up. Is the Enable pin a power-good signal?

kind regards,

Elliott Dexter 

mattlenz
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Yes, POWER ENABLE is a power

Yes, POWER ENABLE is a power-good signal AFAIK. It may be directly connected to the Power-good for the voltage regulator responsible for VSYS or to a power good further down in the chain of the motherboard.

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Hi Matthias,

Hi Matthias,

The reason why i suggest you move the PWR_UP flag is so that when going the PMIC goes back down the sequeincer, there isnt transisiton issue due to the PMIC trying to transisiton from two different states.

Kind regards,
Elliott

mattlenz
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Thanks for the hint.

Thanks for the hint.