DA9063 : External DC/DC Converter

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A. Ott
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DA9063 : External DC/DC Converter

Hi

I'm working on a DA9063 Design with an additional external 3.3V Converter.
I added a attachment with a simplified Power Tree and Timing Diagram.

The external 3.3V DC/DC Converter has an Enable and a Power Good Signal.
I want that the DA9063 enables after Startup the 3.3V Enable Signal and waits until the 3.3V PG Signal is given.
After that the DA9063 should start with his own Power Sequencing.

When the 3.3V PG Signal is lost the DA9063 should make a reset and sould restart as before.
Also the 3.3V Regulator should be disabled and restartet again.

To get to this behaviour I planned to use a GPIO as the 3.3V Enable signal and the System_EN is connected to the 3.3V PG Signal.
I thought it would be the right decision to enable the GPIO 3.3V Enable Signal in Sequencer Time Slot 0.
So the DA9063 has to wait until the PG Signal is set and after that starts with his power sequence.
And when the 3.3V Supply fails the PG Signal disables the System_EN which creates a reset.

Questions:
Is this the right way to realise my intended behaviour?
I'm not shure if at a reset the Slot 0 : 3.3V Enable signal will be toggled so that the 3.3V Supply does also a reset?
Should the 3.3V Enable GPIO "Fall Slot" defined as Slot 1 or is Slot 0 the right one?

Best Regards
Alex

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ED_Dialog
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Hello Alex,

Hello Alex,

  1. The DA9063 has GPIOs that can be configured to behave in the way that you described. GPIO8 and GPIO9 have functions suitable for this operation. GPIO8 can be configured to be a Hardware enable signal GPI and GPIO9 can be configured to be a power good signal GPI. 
  2.  Slot 0 should only be used/set if you wish for that regulator or function not to be turned on.

 

Turning the DA9063 PMIC on in the way you describe is possible; we just require some more information on the restart: 

  1. What causes the PG signal loss?
  2. When the DA9063 restarts, do you require it go back down the sequencer?
  3. Should the DA9063 restart the 3.3 V external regulator?
  4. How does the external 3.3 V regulator restart?
  5. Do you have any further details on how you would like the system to restart?

Kind Regards,

Elliott Dexter 

A. Ott
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Hi Elliott

Hi Elliott

Thanks for your reply.

1. Yes I also intended to use GPIO8 and GPIO9. So we got the same idea

3. a PG loss could be caused by a short at the output of the Supply. I have the situatiuon in mind where I'm at measuring stuff on the board and unintentionally short the output of my external 3.3V supply. In that case all supplies from the DA9063 should also turn-off. This becuause we got IC's on the board which die when the 3.3V Supply Rail goes below the 1.8V Rail (from DA9063)
4. If possible a fast shutdown.
5. Yes
6. Toggle it's enable signal
7. auto-boot mode

Regards Alex

ED_Dialog
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Hi Alex, 

Hi Alex,

 

3. If the DA9063 loses its PG signal from the external regulator, the DA9063 will go into SYSEN mode and will not reset, the DA9063 will then wait for a SYS_EN signal. Regulators will still be turned on in this mode.

4. A fast shutdown is possible, Register bit INT_SD_MODE, can either be set to normal or too fast. Fast will skip the sequencer and any dummy slots.

6. This could be achieved by a GPIO set as a GPO, or a low current LDO. The LDO can be set to switch between 0 V and a selected voltage.

7. The DA9063 has an Autoboot setting. 

Kind Regards,

Elliott Dexter 

A. Ott
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Hi Elliott

Hi Elliott

I think we might not understand each other.

The Datasheet states clearly that when SYS_EN with nRES_MODE active is deasserted
the DA9063 triggers a power down sequence into standby mode and deactivates all Regulators without xxxx_CONF asserted

I think you meant something different with answer 3.

Maybe from the beginning:

I intended to connect the 3V3_EN to "Random GPIO" as example GPIO9 and use Connect the 3V3_PG to GPIO8/SYS_EN and configure it as SYS_EN

Problem : I have to set 3V3_EN before SYS_EN is present
Solution : Use Slot 0 to control (in this case) GPIO9
follow up problem : 3V3_EN never gets toggled so my intended behaviour is not satisfied.

My question is : how can I implement my intended behaviour or is this not possible with the DA9063?
Or do I have to design an external circuit which implements this behaviour?

---
As an alternative i could use the feature from GPIO10 with a WAIT_STEP.
So I would use the autoboot mode and connect the 3V3_EN Signal to a random GPIO as example GPIO9 and also I would connect 3V3_PG to GPIO10.
Then I would start with GP_RISE4_STEP in Slot 1 and WAIT_STEP in Slot 2.

Problem : But When I get it right, then when I lost 3V3_PG signal nothing would happen.
so this time my main intention would be unsatisfied...

to use the 3V3_PG signal as example the shutdown signal would be totally wrong because 3V3_PG will actively pull to gnd until the output voltage will reach 3.3V

---
I don't know. I think I overlook a basic feature which would implement my intended behavior.
But I don't find it in the datasheet

I would be very grateful if you could point me into the right direction

Sincerely Alex

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Hi Alex,

Hi Alex,

I think the confusion came from the first bit, i assumed you were planning on connecting the 3V3_EN to GPIO8/SYS_EN and your 3V3_PG to GPIO9/PWR_EN, in this setup, if GPIO9 loses the PG signal and toggles the pin the PMIC will go into SYS mode. What are you using to trigger the GPIOs, is it the output from the external regulator or does the external regulator have a GPIOs?

Kind Regards,

Elliott Dexter  

A. Ott
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Hi Elliott

Hi Elliott

I made a PDF with our circuit.
You see on top the 3.3V Regulator and below the (DRAFT) DA9063 (only control and GPIO stuff)

The 3.3V Regulator has en Enable signal with CMOS logic and a Power Good Signal which is an open drain circuit that pulls to GND when the output is not in 10% range of the intended output voltage.

We also got a 5V Main Power Supply which is not shown.

Intended behaviour:
1) DA9063 turns-on 3.3V Regulator before all DA9063 Supplies
2) DA9063 turns-off 3.3V Regulator when its going to Power-Down mode
3) A PG_3V3 lost (PG_3V3 = GND) should trigger the DA9063 to go in Power-Down mode with fast-shutdown
4) A Power failure of any DA9063 supply should trigger a turn-off of the 3.3 Regulator and the DA9063

What do I have to do for this?

Sincerely Alex

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ED_Dialog
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Hi Alex,

Hi Alex,

After viewing your schematic I can see two ways in which you can achieve the operation that you require. I think its best if we make use of the power sequencer, the signal from the DA9063 that enables the MP2147, can come from GPIO8 set as an output. The Step for GPIO8 can be set in the power sequencer before SYSTEM_END, this will toggle the MP2147 enable pin and then wait for the power good signal. The MP2147 will then toggle the DA9063s GPIO9 configured a PWR_EN input, after this is toggled the DA9063 will continue up the sequencer and enable all the other rails (LDOs, BUCKs, GPIOs…etc).  In regards to your schematic this will mean you will have to swap your GPIO8 and GPIO9 rails. Does this make sense?

You have connected LEDs to GPIO10 and GPIO11, these pins can only sink 11 mA, is this enough current for your LEDs?

Kind Regards,

Elliott Dexter  

A. Ott
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Hi Elliott

Hi Elliott

I made some test with the Development Board and I finally realized that I cant fulfill my requirements with the DA9063 alone.
In your solution a failing 3V3 Regulator would not initiate a full reset.

So I modified the circuit.
You see it in the attachment.
I added a driver with en output enable signal, so I can gate the PG Signal from my 3V3 Regulator

1) At startup SHUTDOWN_OE = VSYS (so that I dont end up in a Bootloop)
2) In System Domain I enable the EN_3V3 signal with GPIO8
3) I use the PG_3V3 Signal as PWR_EN Signal.
4) As first Step in Power Domain I pull SHUTDOWN_OE to GND
this enables the shutdown logic.
5) enable all other supplies in Power Domain.

With this modification I should be able to fulfill all of my requirements.

Do you see any downside of this solution?
Also the question in the yellow note : Could I end up in a boot-loop, when I configure the GPIO10 as OD with Pull-Up and delete the external pull-up at the input of the 74LVC1G125?
Because the OTP Settings are loaded after exiting RESET Mode and I assume if nShutdown is pulled the hole time, the DA9063 stays in the Reset Mode?

PS: no the LED's where a copy paste artifact

ED_Dialog
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Hi Alex,

Hi Alex,

I will talk to the application team here. When you say you have a development board, are you using a Dialog DA9063 Evaluation board (44-179-176-05-B) with a daughter board or are you using custom board and have you downloaded the DA9063 GUI?

Kind Regards,

Elliott Dexter 

A. Ott
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Hi Elliott

Hi Elliott

Motherbaord: 44-179-176-05-B
Daughterboard: 44-179-176-07-B

With the delivered SW: DA9063B_3v1 : 3.1.0.458 SVN

Regards
Alex

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Hello Alex,

Hello Alex,

What do you intended to use to pulldown the SHUTDOWN_IO? Im just following the logic of the driver.

Kind Regards,

Elliott Dexter 

A. Ott
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Its drawn in the PDF : GPIO10

Its drawn in the PDF : GPIO10
used as a GPO Open Drain.

The logic behind it:
- The 3V3 Regulator will Pull 3V3_PG to GND until the 3V3 output will reach 3.3V.
- So i have to mask the nShutdown signal. Otherwise the DA9063 would not start up
- DA9063 enables the 3V3 Regulator with 3V3_EN = OD not pulling (external Pull Up to VSYS)
- When the 3V3 is started by the DA9063, I will pull GPIO10 to GND to enable the 74LVC1G125. At that Moment 3V3_PG is = VSYS

- When now a 3V3 Fault condition happens : 3V3_PG will get pulled to GND : The output of 74LVC1G125 is getting pulled to GND and so nShutdown will get asserted => Reset

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Hi Alex,

Hi Alex,

The schematic and logic are fine and should fit the operation that you require. To answer your previous two questions:

1) The Pull-up for GPIO10 can be used to pull the line up to 3.3 V , but the bit will have to be cleared when the driver requires OE to be pulled to low, this will effectively arm the reset. Does this make sense?

2) The DA9063 should not stay in reset mode because of the continuous assertion of the nSHUTDOWN in this system, the nSHUTDOWN is edge triggered and not level. 

Kind Regards,

Elliott Dexter 

A. Ott
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Hi Elliott

Hi Elliott

1) In my eye's yes. The OE~ is negative active.
2) I tried it out with the Development Board.
It does not restart, when I pull the nShutdown signal to GND.
I have to release the signal so that the DA9063 does start up again.

Your answer is wrong. ಠ_ಠ

I found an interesting section int the Datasheet:
"Other RESET triggers such as via port nOFF or nSHUTDOWN need to be released before the DA9063 can move
from RESET to POWERDOWN mode"

I'm done with the schematic and we will peer review it in our dev. group.
please close this thread.

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Hi Alex, 

Hi Alex, 

We cannot find "Other RESET triggers such as via port nOFF or nSHUTDOWN need to be released before the DA9063 can move
from RESET to POWERDOWN mode" in the current data sheet 2v1.  We can find:

"● Forced from the host processor (non-interruptible) by:

○ asserting port nSHUTDOWN (falling edge)

○ writing to register bit SHUTDOWN”

Are you using the up to date datasheet? We tested the configuration, by holding the nSHUTDOWN low and DA9063 started.

2) It sounds like you have attempted to use nSHUTDOWN after power up and that would require nSHUTDOWN to be released. In our test nSHUTDOWN was held low (GND) at application of power to the system. 

 

Kind Regards,

Elliott Dexter 

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Hi Elliott

Hi Elliott

1) Its on the next page as your copied text.
Page 70 DA9063_2v1 23-Mar-2017

2) Yes of course i used nSHUTDOWN after a power up. That is the use-case I tried to explain.
==> A failure of the external 3V3 Voltage Regulator should force a reset of the DA9063 otherwise IC's in the board get damaged.
After that a normal system restart.
And of course the DA9063 at this moment is still powered from VSYS from the 5V0 Regulator.

I tried several times to explain what I want to achieve.
When I'm not explicit enough... fine. English is not my native language
But lets close this discussion I wasted too much time already.

Regards
Alex

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