SLAVE behavior with SPI_BUSY bit in SPI_CTRL_REG1

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BarryReinhold
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SLAVE behavior with SPI_BUSY bit in SPI_CTRL_REG1

The SPI_BUSY bit is documented a Table 165 as being "busy" (The SPI is busy with a transfer) when set.
When SPI_BUSY is reset it implies one of two conditions, (a) No TX data is available, or (b) RX-FIFO is full.
Is it the case that SPI_BUSY is set if and only if [TX data is available or RX-FIFO is full]?

The reason I ask is in spi.c there is the following code for writing a byte

__INLINE void spi_write_byte(uint8_t wr_byte)
{
while (GetBits16(SPI_CTRL_REG,SPI_TXH)==1); // Wait if SPI Tx FIFO is full
SetWord16(SPI_RX_TX_REG0, 0xFF&wr_byte); // Send byte
while (GetBits16(SPI_CTRL_REG1,SPI_BUSY)==1); // Wait while SPI is busy
GetWord16(SPI_RX_TX_REG0);

What is the purpose of the line: while (GetBits16(SPI_CTRL_REG1,SPI_BUSY)==1); // Wait while SPI is busy
before the GetWord16? If SPI_BUSY being set implies that there is either TX data available, or the RX-FIFO is full why would one wait before doing the GetWord?
If SPI_BUSY being set indicates something else, what is it?