I found below paraprarh in DA14580 datasheet.
1 = The SPI has high priority, DMA request signals remain
active until the FIFOS are filled/emptied, so the DMA holds
the AHB bus.
But I do not clearly understand about this meanings.
Our concern is below.
If application send data whose size is more than FIFO TX buffer,I worry that timing of SPI transmission may be disrupted when ble event occurred,because interruption of BLE is higher priority than SPI.
I would like to transmit SPI data with precisely same clock timing.
It seems when ble event make M0-CPU be interrupted,so this period cpu cannot send data to SPI .In interrupt period only the data which is buffered in FIFO TX buffer can be send.
Is this thoughts correct?
So,I want to know below questions.
1)How many buffer as FIFO TX?
2)And in DMA active period (while data in FIFO TX buffer is transmitting ) when ble event is occurred , would transmission of the data be interrupted?
3)When ble event is occurred and make M0-CPU be interrupted ,how many seconds CPU is interrupted ? how many seconds is needed until SPI communication can restart.